Zephyr GEM Driver Support

This page gives an overview of the GEM (Gigabit Ethernet MAC) Zephyr driver, which ships as part of the zephyr-amd repository.

Introduction

This page offers detailed information about the Zephyr GEM driver. The driver enables GEM support on Versal Gen 2 SoCs, for both the APU and the RPU.

HW Features

The GEM is a hard-IP PS peripheral with its own internal DMA engine that manages receive and transmit buffer descriptor rings.

For further details, refer to the GEM Ethernet chapter in the Versal Gen 2 Technical Reference Manual (AM026).

Design Notes

  • The GEM has its own internal DMA engine that manages the receive and transmit buffer descriptor rings.

  • The transmit clock is derived from the SoC PLL, and the divider values are reconfigured at runtime whenever the PHY-reported link speed changes.

Features Supported

  1. 1G PHY interface using RGMII

  2. 1000 Mb/s link speed

  3. PHY management through the integrated MDIO bus

Missing Features

  • No support for VLAN frames

  • No support for PTP

  • No jumbo frame support

Known Issues

  • N/A

Limitations

  • Performance benchmarking is not completed.

Kernel Configuration

The following DMA and Ethernet kernel configurations are needed:

CONFIG_ETH_DRIVER=y
CONFIG_NET_L2_ETHERNET=y
CONFIG_ETH_XLNX_GEM=y
CONFIG_MDIO_XLNX_GEM=y

Device Tree

GEM node:

gem0: ethernet@f1a60000 {
    compatible = "xlnx,gem-controller";
    status = "okay";
    reg = <0x0 0xf1a60000 0x0 0x1000>;

    gem0_mac: ethernet_mac {
        compatible = "xlnx,gem";
        status = "okay";
        clock-frequency = <0x7735464>;
        interrupts = <0x0 0x27 0x4 0xa0 0x0 0x27 0x4 0xa0>;
        amba-ahb-burst-length = <0x10>;
        hw-rx-buffer-size = <0x3>;
        hw-rx-buffer-offset = <0x0>;
        hw-tx-buffer-size-full;
        rx-buffer-descriptors = <0x20>;
        tx-buffer-descriptors = <0x20>;
        rx-buffer-size = <0x600>;
        tx-buffer-size = <0x600>;
        discard-rx-fcs;
        unicast-hash;
        local-mac-address = [00 0A 35 00 01 02];
    };
};

MDIO and PHY node:

&gem0 {
    gem0_mac: ethernet_mac {
        phy-handle = <&phy0>;
    };

    gem0_mdio: mdio {
        compatible = "xlnx,gem-mdio";
        status = "okay";
        #address-cells = <1>;
        #size-cells = <0>;

        phy0: ethernet-phy@1 {
            reg = <0x1>;
            compatible = "ti,dp83867";
            ti,rx-internal-delay = <0x8>;
            ti,tx-internal-delay = <0xa>;
            ti,interface-type = "rgmii-id";
            status = "okay";
        };
    };
};

Driver Stack Size

  • TBA

Test Platform

  • Versal Gen 2

Test SoC Architecture

Testing Sequence

  • Build a Zephyr application for the A78 or R52 core

    • west build -p -b <board> <sample application path>

  • Run the Zephyr ELF on the target board.

Example Tests

Test Name

Example Source

Description

dhcpv4_client

samples/net/dhcpv4_client/

Starts a DHCPv4 client, gets an IPv4 address from the DHCPv4 server, and prints the address, lease time, netmask, and router information to a serial console.

echo_server

samples/net/sockets/echo_server

Implements a UDP/TCP server that listens for incoming IPv4 or IPv6 packets sent by the echo client and sends them back.

raw_packet

samples/net/sockets/packet

A simple packet socket application showing usage of packet sockets over Ethernet. It prints every packet received and sends a dummy packet every five seconds.

http_client

samples/net/sockets/http_client

Implements an HTTP or HTTPS client that performs an HTTP or HTTPS request and waits for the response from the HTTP server.

Expected Output

DHCPv4 client (west build -p -b <board> samples/net/dhcpv4_client/):

[00:00:00.003,000] <inf> phy_ti_dp83867: TX FIFO depth is set to 4 bytes/nibbles
[00:00:00.004,000] <inf> net_dhcpv4_client_sample: Run dhcpv4 client
[00:00:00.004,000] <inf> net_dhcpv4_client_sample: Start on ethernet_mac: index=1
[00:00:03.505,000] <inf> phy_ti_dp83867: PHY 1 is up
[00:00:03.505,000] <inf> phy_ti_dp83867: PHY (1) Link speed 1000 Mb, full duplex
[00:00:08.007,000] <inf> net_dhcpv4: Received: 10.10.70.1
[00:00:08.007,000] <inf> net_dhcpv4_client_sample: Address[1]: 10.10.70.1
[00:00:08.007,000] <inf> net_dhcpv4_client_sample: Subnet[1]: 255.255.255.0
[00:00:08.007,000] <inf> net_dhcpv4_client_sample: Router[1]: 10.10.70.101
[00:00:08.007,000] <inf> net_dhcpv4_client_sample: Lease time[1]: 600 seconds

Echo server (west build -p -b <board> samples/net/sockets/echo_server):

[00:00:00.004,000] <inf> phy_ti_dp83867: TX FIFO depth is set to 4 bytes/nibbles
[00:00:00.004,000] <inf> net_config: Initializing network
[00:00:00.004,000] <inf> net_config: IPv4 address: 10.10.70.13
[00:00:00.105,000] <inf> net_echo_server_sample: Run echo server
[00:00:00.105,000] <inf> net_echo_server_sample: Waiting for TCP connection on port 4242 (IPv4)...
[00:00:03.506,000] <inf> phy_ti_dp83867: PHY 1 is up
[00:00:03.506,000] <inf> phy_ti_dp83867: PHY (1) Link speed 1000 Mb, full duplex
[00:00:51.673,000] <inf> net_echo_server_sample: TCP (IPv4): Accepted connection
[00:00:55.098,000] <dbg> net_echo_server_sample: handle_data: TCP (IPv4): Received and replied with 8 bytes

Raw packet (west build -p -b <board> samples/net/sockets/packet):

[00:00:00.003,000] <inf> phy_ti_dp83867: TX FIFO depth is set to 4 bytes/nibbles
[00:00:03.505,000] <inf> phy_ti_dp83867: PHY 1 is up
[00:00:03.505,000] <inf> phy_ti_dp83867: PHY (1) Link speed 1000 Mb, full duplex
[00:01:25.006,000] <dbg> net_pkt_sock_sample: send_packet_socket: Sent 100 bytes
[00:01:27.781,000] <dbg> net_pkt_sock_sample: recv_packet_socket: Received 46 bytes
[00:01:30.006,000] <dbg> net_pkt_sock_sample: send_packet_socket: Sent 100 bytes

Performance Metric

  • TBA

Mainline Status

Driver Source Path

  • drivers/ethernet/eth_xlnx_gem.c

MISRA C Report