Zephyr AXI Ethernet Driver Support
This page gives an overview of the AXI Ethernet Zephyr driver which is available as part of the zephyr-amd repo.
Introduction
The AXI 1G/2.5G Ethernet Subsystem core is a soft IP core for use with Vivado Design Suite. The AXI Ethernet Subsystem implements a tri-mode (10/100/1000 Mb/s) Ethernet MAC or a 10/100 Mb/s Ethernet MAC. This core supports the use of MII, GMII, SGMII, RGMII, and 1000BASE-X interfaces to connect a media access control (MAC) to a Physical-side interface (PHY) chip. It also provides an on-chip PHY for 1G/2.5G SGMII and 1000/2500 BASE-X modes. The MDIO interface is used to access PHY Management registers. This subsystem optionally enables TCP/UDP full checksum Offload, VLAN stripping, tagging, translation, and extended filtering for multicast frames features.
For more information, refer to the AXI Ethernet product page which includes links to the official documentation and resource utilization.
Hardware Features
Axi Ethernet Controller: AXI Ethernet product page
Design Notes
An AXI Ethernet + AXI DMA design is needed to verify the Ethernet applications.
Implementation
Features Supported
The AXI Ethernet Zephyr driver supports the following features:
Supports 1G phy-interface types RGMII
Support for AXI DMA Ethernet-based designs
Supports different Speeds 10/100/1000 Mb/s
Supports Partial/Full Checksum offloading
Missing Features
No Support for VLAN Frames
No support for PTP
No Jumbo Frame Support
No Support for Axi MCDMA Ethernet-based designs
Known Issues
N/A
Limitations
Performance Benchmarking is not completed
Kernel Configuration
The Following DMA and Ethernet kernel Configurations are needed:
CONFIG_DMA=y
CONFIG_ETH_DRIVER=y
CONFIG_NET_L2_ETHERNET
Device Tree
AXI Ethernet Node
axi_enet: axi-ethernet-subsystem@40c00000 {
phandle = <0x8>;
status = "okay";
compatible = "xlnx,axi-ethernet-subsystem-7.2";
reg = <0x40c00000 0x40000>;
axi_ethernet: ethernet-mac {
phandle = <0x13>;
compatible = "xlnx,axi-ethernet-1.00.a";
interrupt-parent = <µblaze_0_axi_intc>;
interrupts = <0x5 0x2 0x4 0x0>;
axistream-connected = <&axi_ethernet_0_dma>;
axistream-control-connected = <&axi_ethernet_0_dma>;
local-mac-address = [00 0a 23 00 00 00];
xlnx,rxcsum = <0x0>;
xlnx,txcsum = <0x0>;
};
};
AXI DMA Node
axi_ethernet_0_dma: dma@41e00000 {
phandle = <0xb>;
dma-channels = <0x2>;
status = "okay";
xlnx,include-dre;
xlnx,addrwidth = <0x20>;
reg = <0x41e00000 0x10000>;
#dma-cells = <0x1>;
interrupt-parent = <µblaze_0_axi_intc>;
clock-frequency = <0x5f5e100>;
compatible = "xlnx,eth-dma";
interrupts = <0x6 0x2 0x7 0x2>;
};
MDIO and PHY Node
&axi_enet {
axi_ethernet: ethernet-mac {
phy-handle = <&axi_ethernetphy1>;
};
axi_ethernet_mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "xlnx,axi-ethernet-1.00.a-mdio";
axi_ethernetphy1: phy@1 {
device_type = "ethernet-phy";
compatible = "ti,dp83867";
ti,rx-internal-delay = <3>;
ti,tx-internal-delay = <3>;
ti,interface-type = "rgmii-id";
reg = <1>;
};
};
Driver Stack Size
TBA
Testing Sequence
Build the zephyr application for the target core
west build -p -b <board> <sample application path>
Run the Zephyr ELF on the board
Example Tests
Test Name |
Example Source |
Description |
|---|---|---|
dhcp4_client |
samples/net/dhcpv4_client/ |
This application starts a DHCPv4 client, gets an IPv4 address from the DHCPv4 server, and prints address, lease time, netmask, and router information to a serial console. |
echo_server |
samples/net/sockets/echo_server |
The echo-server example application for Zephyr implements a UDP/TCP server that complements the echo-client example application: the echo-server listens for incoming IPv4 or IPv6 packets (sent by the echo client) and simply sends them back. |
raw_packet |
samples/net/sockets/packet |
This example is a simple packet socket application showing usage of packet sockets over Ethernet. The example prints every packet received, and sends a dummy packet every 5 seconds. The Zephyr network subsystem does not touch any of the headers (L2, L3, etc.). |
http_client |
samples/net/sockets/http_client |
This example application implements an HTTP or HTTPS client that issues a request and waits for the response from the HTTP server. |
Expected Output
dhcp_client:west build -p -b <board> samples/net/dhcpv4_client/
I: Enabling IRQ!
I: No IRQs defined!
I: Enable MDIO Bus assuming ethernet clock frequency 2500000 divider 1!
I: MDIO ready!
I: RX Checksum offloading disabled
I: TX Checksum offloading disabled
I: Soft-resetting the DMA core!
I: Completed configuration of AXI DMA - Starting transfer!
I: Link state changed to: down (speed 0)
I: Interface initialized!
*** Booting Zephyr OS build xilinx_v2024.2-116-gb6db2ef61eb4 ***
I: Run dhcpv4 client
I: Start on ethernet-mac: index=1
uart:~$ I: PHY 1 is up
I: PHY (1) Link speed 1000 Mb, full duplex
I: Link state changed to: up (speed 20)
I: Completed configuration of AXI DMA - Starting transfer!
I: Received: 192.0.2.20
I: Address[1]: 192.0.2.20
I: Subnet[1]: 255.255.255.0
I: Router[1]: 192.0.2.1
I: Lease time[1]: 600 seconds
echo_server:west build -p -b samples/net/sockets/echo_server
I: Enabling IRQ!
I: No IRQs defined!
I: Enable MDIO Bus assuming ethernet clock frequency 2500000 divider 1!
I: MDIO ready!
I: RX Checksum offloading disabled
I: TX Checksum offloading disabled
I: Soft-resetting the DMA core!
I: Completed configuration of AXI DMA - Starting transfer!
I: Link state changed to: down (speed 0)
I: Interface initialized!
I: Completed configuration of AXI DMA - Starting transfer!
*** Booting Zephyr OS build xilinx_v2024.2-116-gfa458ddda840 ***
I: Initializing network
I: IPv4 address: 192.0.2.30
uart:~$ I: IPv6 address: 2001:db8::1
I: Run echo server
I: Network connected
I: Starting...
I: Waiting for TCP connection on port 4242 (IPv6)...
I: Waiting for TCP connection on port 4242 (IPv4)...
I: Waiting for UDP packets on port 4242 (IPv6)...
I: Waiting for UDP packets on port 4242 (IPv4)...
I: PHY 1 is up
I: PHY (1) Link speed 1000 Mb, full duplex
I: Link state changed to: up (speed 20)
I: TCP (IPv4): Accepted connection
I: Waiting for TCP connection on port 4242 (IPv4)...
D: TCP (IPv4): Received and replied with 8 bytes
I: IPv4 TCP: Received 0 B/sec
D: TCP (IPv4): Received and replied with 11 bytes
I: IPv4 TCP: Received 0 B/sec
D: TCP (IPv4): Received and replied with 5 bytes
D: TCP (IPv4): Received and replied with 3 bytes
I: TCP (IPv4): Connection closed
I: TCP (IPv4): Accepted connection
I: Waiting for TCP connection on port 4242 (IPv4)...
D: TCP (IPv4): Received and replied with 8 bytes
D: TCP (IPv4): Received and replied with 11 bytes
I: TCP (IPv4): Connection closed
I: IPv4 TCP: Received 0 B/sec
D: (udp4): UDP (IPv4): Received and replied with 6 bytes
I: IPv4 UDP: Received 0 B/sec
D: (udp4): UDP (IPv4): Received and replied with 11 bytes
D: (udp4): UDP (IPv4): Received and replied with 3 bytes
D: (udp4): UDP (IPv4): Received and replied with 5 bytes
I: IPv4 UDP: Received 0 B/sec
raw_packet:west build -p -b samples/net/sockets/packet
I: Enabling IRQ!
I: No IRQs defined!
I: Enable MDIO Bus assuming ethernet clock frequency 2500000 divider 1!
I: MDIO ready!
I: RX Checksum offloading disabled
I: TX Checksum offloading disabled
I: Soft-resetting the DMA core!
I: Completed configuration of AXI DMA - Starting transfer!
I: Link state changed to: down (speed 0)
I: Interface initialized!
*** Booting Zephyr OS build xilinx_v2024.2-214-g186b1fd603f9 ***
I: Packet socket sample is running
I: Waiting for packets ...
I: Completed configuration of AXI DMA - Starting transfer!
D: Sent 100 bytes
uart:~$ I: PHY 1 is up
I: PHY (1) Link speed 1000 Mb, full duplex
I: Link state changed to: up (speed 20)
D: Sent 100 bytes
D: Sent 100 bytes
D: Sent 100 bytes
D: Received 284 bytes
D: Received 284 bytes
D: Sent 100 bytes
D: Sent 100 bytes
D: Sent 100 bytes
D: Received 284 bytes
D: Received 284 bytes
D: Sent 100 bytes
D: Sent 100 bytes
D: Sent 100 bytes
D: Received 284 bytes
D: Received 284 bytes
http_client:west build -p -b samples/net/sockets/http_client
AXI Ethernet http_client log
I: Enabling IRQ!
I: No IRQs defined!
I: Enable MDIO Bus assuming ethernet clock frequency 2500000 divider 1!
I: MDIO ready!
I: RX Checksum offloading disabled
I: TX Checksum offloading disabled
I: Soft-resetting the DMA core!
I: Completed configuration of AXI DMA - Starting transfer!
I: Link state changed to: down (speed 0)
I: Interface initialized!
*** Booting Zephyr OS build xilinx_v2024.2-121-g3191fb0f08f8 ***
I: Initializing network
I: IPv4 address: 192.168.14.10
uart:~$ I: Completed configuration of AXI DMA - Starting transfer!
I: PHY 1 is up
I: PHY (1) Link speed 1000 Mb, full duplex
I: Link state changed to: up (speed 20)
D: Data to send
D: 47 45 54 20 2f 20 48 54 |GET / HT
D: 54 50 2f 31 2e 31 0d 0a |TP/1.1..
D: 48 6f 73 74 3a 20 31 39 |Host: 19
D: 32 2e 31 36 38 2e 31 34 |2.168.14
D: 2e 32 34 0d 0a 0d 0a |.24....
D: (main): Sent 39 bytes
D: (main): -- HTTP GET response (headers) --
D: (main): HTTP response status 200 OK
D: (main): [6] Server
D: (main): [28] SimpleHTTP/0.6 Python/3.12.3
D: (main): [4] Date
D: (main): [29] Fri, 30 May 2025 10:44:20 GMT
D: (main): [12] Content-type
D: (main): [9] text/html
D: (main): [14] Content-Length
D: (main): [3] 178
D: (main): [13] Last-Modified
D: (main): [29] Wed, 11 Dec 2024 20:32:32 GMT
D: (main): Headers complete
D: (main): Processed 178 length 178
D: (main): -- HTTP GET response (complete) --
D: (main): Calling callback for 364 len data
I: All the data received (364 bytes)
I: Response to IPv4 GET
I: Response status OK
D: (main): Received 364 bytes
I: http_client_req completed for HTTP_GET / IPv4 GET
D: Data to send
D: 50 4f 53 54 20 2f 66 6f |POST /fo
D: 6f 62 61 72 20 48 54 54 |obar HTT
D: 50 2f 31 2e 31 0d 0a 48 |P/1.1..H
D: 6f 73 74 3a 20 31 39 32 |ost: 192
D: 2e 31 36 38 2e 31 34 2e |.168.14.
D: 32 34 0d 0a 43 6f 6e 74 |24..Cont
D: 65 6e 74 2d 4c 65 6e 67 |ent-Leng
D: 74 68 3a 20 36 0d 0a 0d |th: 6...
D: 0a |.
I: http_client_req completed for HTTP_POST /foobar IPv4 POST
D: Data to send
D: 50 4f 53 54 20 2f 63 68 |POST /ch
D: 75 6e 6b 65 64 2d 74 65 |unked-te
D: 73 74 20 48 54 54 50 2f |st HTTP/
D: 31 2e 31 0d 0a 48 6f 73 |1.1..Hos
D: 74 3a 20 31 39 32 2e 31 |t: 192.1
D: 36 38 2e 31 34 2e 32 34 |68.14.24
D: 0d 0a 54 72 61 6e 73 66 |..Transf
D: 65 72 2d 45 6e 63 6f 64 |er-Encod
D: 69 6e 67 3a 20 63 68 75 |ing: chu
D: 6e 6b 65 64 0d 0a 0d 0a |nked....
D: (main): Sent 117 bytes
D: (main): -- HTTP POST response (headers) --
D: (main): HTTP response status 200 OK
D: (main): [6] Server
D: (main): [28] SimpleHTTP/0.6 Python/3.12.3
D: (main): [4] Date
D: (main): [29] Fri, 30 May 2025 10:44:21 GMT
D: (main): [12] Content-Type
D: (main): [9] text/html
D: (main): [14] Content-Length
D: (main): [2] 24
D: (main): Headers complete
D: (main): Processed 24 length 24
D: (main): -- HTTP POST response (complete) --
D: (main): Calling callback for 163 len data
I: All the data received (163 bytes)
I: Response to IPv4 POST
I: Response status OK
D: (main): Received 163 bytes
Performance Metric
TBA
Mainline Status
Driver Source Path
drivers/ethernet/eth_xilinx_axienet.c
Misra C Report
TBA