Zephyr AXI QSPI Driver Support
This page gives an overview of the AXI QSPI Zephyr driver which is available as part of the zephyr-amd repo.
HW Features
Configurable AXI4 interface; when configured with an AXI4-Lite interface the core is backward compatible with version 1.00 of the core (legacy mode)
Configurable AXI4 interface for burst mode operation for the Data Receive Register (DRR) and the Data Transmit Register (DTR) FIFO
Configurable eXecute In Place (XIP) mode of operation
Connects as a 32-bit slave on either AXI4-Lite or AXI4 interface
Configurable SPI modes:
Standard SPI mode
Dual SPI mode
Quad SPI mode
Programmable SPI clock phase and polarity
Configurable FIFO depth (16 or 256 element deep in Dual/Quad/Standard SPI mode).
Design Notes
TBA
Implementation
Features Supported
Master mode
Sync Mode
Async mode.
All SPI flash Instruction.
Configurable FIFO size.
Startup block support
Missing Features
Dual SPI mode
Quad SPI mode
Known Issues
TBA
Limitations
TBA
Kernel Configuration
/* SPI and flash z-test config */
CONFIG_TEST=y
CONFIG_ZTEST=y
CONFIG_FLASH=y
CONFIG_FLASH_PAGE_LAYOUT=y
CONFIG_MAIN_STACK_SIZE=2048
Device Tree
Example SPI Node
axi_spi0: spi@44a00000 { status = "okay"; #address-cells = <0x01>; #size-cells = <0x00>; fifo-size = <256>; reg = <0x44a00000 0x10000>; compatible = "xlnx,xps-spi-2.00.a"; interrupt-parent = <&axi_intc>; xlnx,startup-block; interrupts = < 3 0 >; xlnx,num-ss-bits = <0x2>; xlnx,num-transfer-bits = <8>; flash@0 { compatible = "jedec,spi-nor"; reg = <0x00>; spi-max-frequency = <8000000>; jedec-id = [20 bb 19]; /* n25q256 */ size = <134217728>; has-dpd; t-enter-dpd = <10000>; t-exit-dpd = <35000>; }; };
Driver Stack Size
TBA
Example Tests
Test Name |
Example Source |
Description |
|---|---|---|
Flash Ztest |
tests/drivers/flash/common/ |
These tests focus on the correct functionality of the flash drivers, covering cases such as:
|
Flash Example test |
samples/drivers/spi_flash/ |
This example application performs basic Erase/Write/ Read on spi-nor flash using Axi-Quad SPI driver |
Code Coverage
TBA
Expected Output / Test Logs
*** Booting Zephyr OS build xilinx_v2024.2-38-g0b6ff6486056 ***
Running TESTSUITE flash_driver
===================================================================
Test will run on device flash@0
START - test_flash_fill
PASS - test_flash_fill in 42.034 seconds
===================================================================
START - test_flash_flatten
PASS - test_flash_flatten in 41.980 seconds
===================================================================
START - test_read_unaligned_address
PASS - test_read_unaligned_address in 1.081 seconds
===================================================================
TESTSUITE flash_driver succeeded
------ TESTSUITE SUMMARY START ------
SUITE PASS - 100.00% [flash_driver]: pass = 3, fail = 0, skip = 0, total = 3 duration = 85.095 seconds
PASS - [flash_driver.test_flash_fill] duration = 42.034 seconds
PASS - [flash_driver.test_flash_flatten] duration = 41.980 seconds
PASS - [flash_driver.test_read_unaligned_address] duration = 1.081 seconds
------ TESTSUITE SUMMARY END ------
===================================================================
PROJECT EXECUTION SUCCESSFUL
*** Booting Zephyr OS build xilinx_v2024.2-26-ged251cbf3a56 ***
flash@0 SPI flash testing
==========================
Perform test on single sector
Test 1: Flash erase
Flash erase succeeded!
Test 2: Flash write
Attempting to write 4 bytes
Data read matches data written. Good!!
Performance Metric
TBA
Mainline Status
Driver Source Path
drivers/spi/spi_xlnx_axi_quadspi.c
Misra C Report
TBA