Glossary

This page collects the acronyms and terms used throughout the AMD Embedded Development Framework (EDF) documentation. Hover any term reference in the prose elsewhere in the docs to see the dotted-underline cue, and click it to jump to the matching entry below.

<BSP type> disk <binary image / image>

Pre-compiled embedded software binary disk image of the relevant BSP.

ACAP

Adaptive Compute Acceleration Platform, AMD’s family designation for the Versal device line that combines PS, programmable logic, and AIE engines on one die.

ADBUS

BDBUS

CDBUS

DDBUS

FTDI MPSSE pin-bank labels. Each FTDI USB-serial chip channel exposes its eight low-byte data pins as ADBUS0-ADBUS7 (channel A), BDBUS0-BDBUS7 (channel B), and so on.

ADMA

Always-on DMA controller in the LPD on Zynq UltraScale+ MPSoC and Versal devices.

AI

Artificial Intelligence; in this documentation typically used as the qualifier in product family names such as “AMD Versal AI Edge” and “AMD Versal AI Core”.

AIE

AI Engine, the array of VLIW vector processors built into AMD Versal devices that provides hardware acceleration for machine-learning and signal-processing workloads.

AL5D

One of the kernel drivers for the VDU video-decode hard block on AMD Versal AI Edge devices. Each VDU instance exposes up to four decoder cores identified in the devicetree as al5d0 through al5d3.

AMBA

Advanced Microcontroller Bus Architecture, the Arm-defined family of on-chip interconnect specifications (AHB, APB, AXI, …) used by AMD adaptive SoC IP.

AMR

Adaptive Management Runtime, the platform software stack that provides modular device management and system bring-up.

APU

Application Processing Unit.

Arm

Arm Holdings, the British semiconductor IP company that develops the Arm processor architecture and the Cortex CPU family.

ASU

Adaptive Steering Unit, the Versal Gen 2 boot processor that runs after the PMC ROM hands off control.

ATCM

A-port Tightly Coupled Memory, the lower-bank TCM attached to a Cortex-R core.

AXI

Advanced eXtensible Interface, the AMBA-defined memory-mapped and streaming interconnect protocol used to connect IP blocks inside AMD adaptive SoC and FPGA designs.

BASE-X

Family of Ethernet physical-layer specifications (1000BASE-X, 2500BASE-X, …) that defines fiber and SFP-style optical links.

BIF

Bootgen Input File (.bif), the AMD Bootgen tool’s script-style description of how to assemble partitions into a PDI or boot.bin.

BIT

AMD Vivado-generated FPGA bitstream file (.bit) that configures the PL fabric of an AMD adaptive SoC or stand-alone FPGA.

BMC

Baseboard Management Controller, an out-of-band processor on a board that provides power-on, sensor, and remote-management services.

BOM

Bill of Materials, the structured list of components on a board (used in this docs set when distinguishing board revisions whose differences are captured in the schematics and BOM rather than the part number).

boot firmware

OSPI / QSPI based initial boot software.

BRAM

Block RAM, the on-chip memory primitive in AMD FPGA fabric.

BSA

Boot Software Architecture, an Arm specification that defines the firmware-to-software boot contract on Arm-based systems.

BSP

BSPs

Board Support Package - hardware and software artifacts needed to build and run embedded software stacks.

BSP base platform

Embedded common platform (CED) configured with EDF programmable logic payload.

BTCM

B-port Tightly Coupled Memory, the upper-bank TCM attached to a Cortex-R core.

CAB

Microsoft Cabinet file (.cab), the archive format used by the fwupd ecosystem to distribute firmware updates.

CBC

Cipher Block Chaining, a block-cipher mode of operation in which each plaintext block is XORed with the previous ciphertext block before encryption.

CDO

Configuration Data Object, the AMD-defined sub-format inside a PDI that carries register writes, NoC programming, and other configuration data consumed by the PLM.

CED

CEDs

Configurable Example Design.

CIPS

Control, Interfaces, and Processing System, the AMD Vivado IP block that configures the Versal PS, PMC, and device-level interfaces such as IPI for an embedded common platform CED.

CMA

Contiguous Memory Allocator, the Linux kernel subsystem that reserves a physically contiguous DMA-capable memory region at boot for use by drivers that cannot scatter-gather.

CMN

Coherent Mesh Network, the on-chip cache-coherent interconnect that links AMD Versal Adaptive SoC compute complexes (APU, RPU, AI Engine) and on-chip peripherals together. Requires explicit per-node initialization before peripheral access from U-Boot or Linux.

CPM

CCIX/PCIe Module, the integrated PCIe controller block on AMD Versal devices; CPM5 is the Versal Premium variant.

CPU

CPUs

Central Processing Unit.

CRC

Cyclic Redundancy Check, the family of integrity checksums used throughout the EDF boot images and update payloads (CRC-16, CRC-32, …).

CVE

Common Vulnerabilities and Exposures, the public catalog of security advisories tracked by MITRE.

CXX

Common abbreviation for the C++ language in toolchain variable names (CXX, CXXFLAGS).

DDR

Double Data Rate, the synchronous DRAM interface that transfers data on both the rising and falling edges of the clock signal. Variants include DDR3, DDR4, DDR5, and low-power LPDDR families.

DES

Data Encryption Standard, a symmetric-key block cipher published by NIST in 1977.

DFX

Dynamic Function eXchange, AMD’s name for the partial-reconfiguration flow that swaps reconfigurable partitions of the programmable logic at runtime.

DHCP

Dynamic Host Configuration Protocol, the IETF standard that lets a network server hand out IP addresses and other network configuration to clients.

DIMM

Dual In-line Memory Module, the standard form factor for desktop and server DRAM modules.

DIP

Dual In-line Package, the through-hole IC package style; in this documentation the term most often refers to a “DIP switch” - a small bank of single-pole switches in a DIP footprint.

DMA

Direct Memory Access, the bus-mastering technique that lets peripherals read and write system memory without CPU intervention. AMD adaptive SoCs implement several variants; see ADMA, GDMA, QDMA, and ZDMA.

DNF

Dandified YUM, the package-management front-end used by Fedora and the Yocto Project’s RPM-based image flow.

DPDK

Data Plane Development Kit, an open-source set of libraries for fast user-space packet processing.

DRAM

Dynamic Random-Access Memory.

DRM

Direct Rendering Manager, the Linux kernel subsystem that mediates GPU access from user space.

DSP

Digital Signal Processor / Digital Signal Processing.

DTB

Devicetree Blob, the compiled binary form of a devicetree.

DTG

Device Tree Generator, the AMD tool that converts a Vivado hardware design into a devicetree source.

DTS

Devicetree Source, the human-readable text format that describes the hardware topology of a system.

DTSI

DTSIs

Devicetree Source Include, a fragment of a devicetree intended to be included from a top-level DTS file.

DUT

Device Under Test, shorthand for the board or SoC being exercised by a test setup.

ECC

Error-Correcting Code; in this documentation usually refers to memory-controller error correction (single-bit correct, double-bit detect) on DDR/LPDDR controllers and on-chip RAMs.

EDF

AMD Embedded Development Framework.

EDF Linux BSP

BSP with support to boot EDF Linux OS on the primary processing system on the target platform. Hardware artifacts typically include the AMD Vivado Design Suite and Vitis software platforms based designs and projects; software stacks typically include boot firmware, bootloaders, Linux kernel, and root filesystem.

EDF Linux disk <binary image / image>

Binary image with items to boot the system to Linux.

EDF Linux distribution

Linux distribution on which AMD Linux images are based.

EDF Linux OS

AMD reference Linux kernel used within the AMD Embedded Development Framework.

EDF Linux package feed

Linux package feed to allow distribution of software and hardware packaged over the air (OTA).

EDF Linux SDK

EDF Linux Software Development Kit

Software toolkit to enable development on the target or on host platforms (cross compile) of applications and drivers compatible with generated Linux images. Example use: Vitis software platforms.

EEPROM

Electrically Erasable Programmable Read-Only Memory.

EFI

Extensible Firmware Interface, the original Intel-defined firmware interface that UEFI extends and standardizes.

EGL

Khronos rendering surface API that bridges a rendering API such as OpenGL ES with the underlying native windowing system.

EL0

EL1

EL2

EL3

Arm AArch64 Exception Levels. EL0 runs unprivileged application code, EL1 hosts the operating system kernel, EL2 hosts a hypervisor, and EL3 runs the secure monitor (typically TF-A).

ELF

Executable and Linkable Format, the standard container format for object files, executables, and shared libraries on most Unix-like systems.

Embedded Common Platform CED

AMD Vivado Design Suite Configurable Example Design used as a common base for AMD EDF BSP creation.

Embedded software

Embedded software stack.

EMIO

Extended Multiplexed I/O, the PS-to-PL GPIO bridge that routes PS peripheral signals through the PL fabric instead of through dedicated package pins.

eMMC

Embedded MultiMediaCard, a managed-NAND flash storage standard defined by JEDEC and soldered onto the host board.

ESP

ESPs

EFI System Partition, the FAT-formatted partition that a UEFI firmware reads boot loaders from.

FAE

Field Application Engineer, an AMD customer-facing technical specialist who provides design guidance, application support, and access to restricted materials for qualified customers.

FAQ

Frequently Asked Questions.

FAT

File Allocation Table, the family of filesystems originally developed for MS-DOS (FAT12, FAT16, FAT32).

FFT

Fast Fourier Transform.

FIFO

First In, First Out, the queue ordering used by hardware buffers throughout the AMD adaptive SoC peripheral set.

FIT

Flattened uImage Tree, the U-Boot multi-image container format that bundles a kernel, devicetree, and optional initramfs into a single signed file.

FMC

FPGA Mezzanine Card, the VITA 57.1 standard for daughter cards that plug into an FPGA carrier board.

FPD

Full-Power Domain, the Zynq UltraScale+ MPSoC power domain that hosts the APU cluster and the high-bandwidth peripherals.

FPGA

Field-Programmable Gate Array, the family of integrated circuits whose internal logic can be reconfigured after manufacture by loading a bitstream.

FSBL

First Stage Boot Loader, the user-supplied boot stage that runs on the APU on Zynq UltraScale+ MPSoC after the BootROM, bringing up the PS, configuring the PL, and launching subsequent firmware (PMU firmware, ATF, U-Boot). On Versal this role is taken over by the PLM.

FTDI

Future Technology Devices International, the Scottish vendor whose USB-serial and MPSSE chips are commonly used for board debug consoles and JTAG bridges.

FWU

Firmware Update; in particular the PSA FWU multi-bank update flow used by the EDF U-Boot configuration.

GBM

Generic Buffer Management, the Mesa-defined API that lets OpenGL / Vulkan clients allocate and share native graphics buffers without going through a window system.

GDMA

General DMA controller in the FPD on Zynq UltraScale+ MPSoC.

GEM

Gigabit Ethernet MAC, the AMD/Cadence Ethernet IP used as the Zynq and Versal primary Ethernet controller.

GIC

Generic Interrupt Controller, the Arm-defined interrupt controller architecture used on Cortex-A and Cortex-R systems.

GLES

OpenGL for Embedded Systems, the Khronos-standardized subset of OpenGL targeted at mobile and embedded GPUs.

GMII

Gigabit Media-Independent Interface, the IEEE 802.3 PHY-to-MAC interface for 1 Gbps Ethernet.

GMIO

Global Memory I/O, the Versal AIE mechanism that moves data directly between the AI Engine array and DDR memory through the Network-on-Chip without involving the PS or PL streaming interfaces.

GPIO

General-Purpose Input/Output, the bit-level digital pin interface exposed both by the PS (MIO/EMIO) and by AXI GPIO IP cores in the PL.

GPT

GUID Partition Table, the partition-table format defined by UEFI as the successor to MBR.

GPU

Graphics Processing Unit; on Zynq UltraScale+ MPSoC and Kria this typically refers to the Arm Mali-400 MP2 in the PS.

GRUB

GRand Unified Bootloader, the GNU multi-platform boot loader.

GTM

Versal Gen 2 multi-rate transceiver tile.

GTYP

Versal Premium high-speed transceiver tile.

GUI

Graphical User Interface.

GUID

GUIDs

Globally Unique Identifier, a 128-bit identifier used by Microsoft (and by GPT and UEFI) to label objects uniquely across systems.

HBM

High-Bandwidth Memory, the JEDEC stacked-DRAM standard integrated on AMD Versal Premium HBM and Alveo V80 devices.

HDMI

High-Definition Multimedia Interface.

I2C

Common spelling of IIC.

IEEE

Institute of Electrical and Electronics Engineers, the international standards body that publishes Ethernet, Wi-Fi, and many other communication standards.

IIC

Inter-Integrated Circuit, also written I2C; a two-wire serial bus used to interconnect low-speed peripherals.

IOP

I/O Peripherals, the cluster of low-speed PS peripherals (UART, I2C, SPI, GPIO, CAN, …) on AMD adaptive SoC devices.

IPC

Inter-Processor Communication, the broader category of mechanisms by which the APU, RPU, and other compute domains exchange data and control. Builds on lower-level primitives such as IPI and shared-memory channels and is exposed to user code by frameworks like OpenAMP and libmetal.

IPI

Inter-Processor Interrupt, the AMD-defined doorbell mechanism that lets the PLM, PSM, APU, and RPU coordinate over a shared message buffer.

IRQ

Interrupt Request, the per-line signal an interrupt source asserts to the GIC.

ISA

Instruction Set Architecture.

ISP

Image Signal Processor, a hardware block that turns raw camera sensor data into a usable image.

ISR

Interrupt Service Routine.

JTAG

Joint Test Action Group, the IEEE 1149.1 boundary-scan and hardware-debug interface used to program and debug AMD adaptive SoCs and FPGAs.

LBA

Logical Block Addressing, the linear-address scheme used by modern block storage devices.

LED

LEDs

Light-Emitting Diode.

libmetal

Open-source low-level abstraction library that hides the differences between Linux user space, Linux kernel space, RTOS, and bare-metal environments behind a single shared-memory / interrupt / device API. Used by OpenAMP as the portable substrate underneath remoteproc and the RPMsg messaging layer; the upstream AMD fork is the libmetal-xlnx Yocto recipe.

LPD

Low-Power Domain, the Zynq UltraScale+ MPSoC power domain that hosts the RPU cluster and the always-on peripherals.

LVFS

Linux Vendor Firmware Service, the public hosting service consumed by fwupd to deliver firmware updates as CAB packages.

MAC

Media Access Control, the data-link sublayer of the OSI model; a “MAC address” is the 48-bit identifier assigned to a network interface at this layer.

MBR

Master Boot Record, the legacy IBM PC partition-table format that stores up to four primary partitions in the first sector of a disk. EDF uses MBR for the distroboot layout on machines that do not enable EFI boot; UEFI defines GPT as its successor.

MII

Media-Independent Interface, the IEEE 802.3 PHY-to-MAC interface for 100 Mbps Ethernet.

MIO

Multiplexed I/O, the dedicated PS package pins that can be muxed to either GPIO or to a fixed PS peripheral. Compare with EMIO.

MISRA

Motor Industry Software Reliability Association; in this documentation, shorthand for the MISRA C-2012 coding guidelines that the EDF Zephyr drivers are audited against.

MMI

Memory-Mapped Interface, the address-mapped peripheral and register-access scheme on AMD Versal devices.

MPSoC

Multi-Processor System on Chip, the AMD Zynq UltraScale+ device family that combines a 64-bit Arm Cortex-A53 APU, a Cortex-R5 RPU, and programmable logic on a single die.

NCR

NoC Connectivity Region (.ncr) file generated by Vivado that describes the NoC solution for an embedded common platform CED.

NoC

Network on Chip, the high-bandwidth on-die interconnect on AMD Versal devices.

NOR

NOR flash, a flash-memory technology that supports random read access and is commonly used for boot ROMs.

NPI

Network Programming Interface, the dedicated PMC configuration channel used to program NoC, DDR memory controller (DDRMC), and other Versal hard-block configuration data.

OCI

Open Container Initiative, the Linux Foundation project that standardizes container image and runtime formats.

OCM

On-Chip Memory, the small low-latency SRAM block in the LPD of AMD adaptive SoC devices.

OOB

Out-of-Box (in the context of the EDF prebuilt image set) or Out-of-Band (in the context of management interfaces such as the BMC).

OP-TEE

Open Portable Trusted Execution Environment, an open-source reference implementation of an Arm TrustZone secure-world OS.

OpenAMP

Open Asymmetric Multi-Processing, the open-source framework that lets a Linux APU and an RTOS or bare-metal RPU lifecycle each other’s firmware (remoteproc) and exchange messages (RPMsg) over shared memory and IPI mailboxes. EDF ships OpenAMP runtime packages and per-board firmware examples through packagegroup-openamp and the matching *-openamp-fw-examples recipes.

OSFP

Octal Small Form-factor Pluggable, a high-density transceiver cage for 400 / 800 Gbps optical links.

OSPI

Octal Serial Peripheral Interface, the eight-wire SPI variant used as a primary boot medium on AMD adaptive SoCs.

OTA

Over-The-Air, in the context of distributing software or firmware updates to deployed devices over a network.

PCIe

Peripheral Component Interconnect Express, the high-speed serial expansion bus standard managed by PCI-SIG.

PDI

Programmable Device Image, the single boot container consumed by the Versal PMC; bundles bitstream, firmware, and configuration data signed by the AMD Bootgen tool.

PHY

Physical-layer transceiver, in particular the off-chip block that turns MII / RGMII / SGMII / GMII digital interfaces into the analog signals driven onto the cable or fiber.

PL

programmable logic

The reconfigurable fabric portion of an AMD adaptive SoC.

PLM

Platform Loader and Manager, the first software to execute on the Versal PMC; loads the boot image partitions and configures the programmable logic.

PMC

Platform Management Controller, the always-on management processor on AMD Versal devices.

PMOD

Peripheral module, the small daughter-card connector standard promoted by Digilent for low-speed FPGA add-ons.

PMUFW

Platform Management Unit firmware, the management-processor software on Zynq UltraScale+ MPSoC (the equivalent of the PLM on Versal).

POR

Power-On Reset, the reset domain that activates as power first reaches the PS.

PS

Processing System

The hard processor system on an AMD adaptive SoC, including the Arm CPU cluster, the high-bandwidth peripherals, and the on-chip interconnect that links them. Distinguished from the PL.

PS-PL

Processing System / Programmable Logic, the boundary between the hard Arm processor system and the reconfigurable fabric on AMD adaptive SoCs.

PSA

Platform Security Architecture, the Arm-led set of specifications that defines a common security baseline for embedded systems.

PSM

Platform Security Module, the secure-management processor on Versal devices.

QDMA

Queue-based DMA, the PCIe-attached DMA engine on AMD adaptive SoCs.

QEMU

Quick EMUlator, the open-source machine emulator used to run EDF Linux and Zephyr images on the host without physical hardware.

QSFP

Quad Small Form-factor Pluggable, the four-channel transceiver cage used for 40 / 100 / 200 Gbps Ethernet links.

QSPI

Quad Serial Peripheral Interface, the four-wire SPI variant used as a primary boot medium on AMD adaptive SoCs.

RAM

Random-Access Memory.

RCDO

Reduced Configuration Data Object, a stripped-down variant of a CDO used when only register writes are needed.

RF

Radio Frequency.

RFDC

RF Data Converter, the integrated ADC/DAC tile on AMD Zynq UltraScale+ RFSoC and Versal RF devices.

RGMII

Reduced Gigabit Media-Independent Interface, a four-bit-wide Ethernet PHY-to-MAC interface that uses both clock edges.

RISC-V

An open-standard reduced-instruction-set computer architecture maintained by RISC-V International.

RNG

Random Number Generator, a hardware or firmware source of cryptographically usable entropy. UEFI/EFI systems expose one via the EFI_RNG_PROTOCOL.

ROM

Read-Only Memory.

RPM

The RPM Package Manager file format used by Red Hat, Fedora, and the Yocto Project’s RPM-based image flow.

RPMsg

Remote Processor Messaging, the message-passing layer of OpenAMP that runs over the virtio rings set up by remoteproc. EDF exposes RPMsg endpoints between Linux on the APU and a Zephyr / FreeRTOS / bare-metal workload on the RPU, including a TTY-backed /dev/ttyRPMSG0 for line-oriented use.

RPU

RPUs

Realtime Processing Unit.

RTL

Register-Transfer Level, the abstraction layer at which hardware designers describe digital logic in HDL such as Verilog or VHDL before synthesis.

RTOS

Real-Time Operating System.

SBI

Supervisor Binary Interface, the RISC-V specification of the runtime environment that S-mode software calls into.

SC

System Controller

Companion processor on AMD evaluation boards that comes up before the primary device on the board and is responsible for power sequencing, clock configuration, boot-mode selection, and service interfaces such as BEAM and the SC UART.

SCP

Secure Copy, the file-copy protocol that runs over SSH.

SCSI

Small Computer System Interface, the command set used by storage stacks (including the Linux UFS stack) to talk to block devices.

SD

Secure Digital, the SD Card Association’s flash-card family; see also SDHC and SDMMC.

SDFEC

Soft-Decision Forward Error Correction, the AMD Versal programmable LDPC/Turbo decoder hard block.

SDHC

Secure Digital High Capacity, the SD Card Association’s extension of the SD card specification to capacities above 2 GB.

SDK

SDKs

Software Development Kit, a self-contained cross-compilation toolchain that targets a specific embedded platform. In the EDF context the term refers to the prebuilt application SDK built from the meta-edf-app-sdk Yocto recipe; see also EDF Linux SDK.

SDMMC

Combined SD and MultiMediaCard host controller; a controller that can drive either an SD card or an eMMC device.

SDRAM

Synchronous Dynamic Random-Access Memory.

SDT

System Device Tree, the multi-domain device-tree variant generated by SDTGen that describes a heterogeneous SoC’s CPUs, memories, and peripherals in one tree.

SFP-DD

Small Form-factor Pluggable - Double Density, a two-channel transceiver cage that doubles SFP port density on a faceplate.

SGMII

Serial Gigabit Media-Independent Interface, a serialized one-pair-per-direction Ethernet PHY-to-MAC interface.

SHEL

Software Hardware Exchange Loop - flow for passing information between hardware and software tool flows.

SLT

System Level Test.

SMA

SubMiniature version A, a 50-ohm threaded RF coaxial connector commonly used for clocks and high-speed signal probing.

SMP

Symmetric Multi-Processing, the OS-scheduler model in which a single Linux kernel image schedules tasks across all APU cores symmetrically.

SoC

System on Chip, an integrated circuit that combines a processor subsystem, memory, and peripherals on a single die. AMD adaptive SoCs additionally integrate programmable logic.

SoM

System on Module, a small circuit board that integrates a SoC plus its memory and core peripherals; AMD’s Kria product line is a SoM family.

SPI

Serial Peripheral Interface, the four-wire master/slave synchronous serial bus standardized by Motorola; see also QSPI and OSPI.

SPL

Secondary Program Loader, the small first-stage U-Boot binary that loads the full U-Boot image on platforms with limited on-chip ROM.

SRAM

Static Random-Access Memory; see also OCM and TCM for the on-chip SRAM blocks on AMD adaptive SoC devices.

SSD

Solid-State Drive.

SSH

Secure Shell, the IETF cryptographic shell protocol used to open remote login and tunnelled connections.

SSID

Service Set Identifier, the human-readable name that identifies an IEEE 802.11 wireless network.

SYSMON

System Monitor, the on-chip telemetry block on AMD Versal and Zynq UltraScale+ that exposes voltage, temperature, and current measurements to firmware and Linux.

TCL

Tool Command Language.

TCM

Tightly Coupled Memory, on-chip RAM directly attached to a CPU core for deterministic-latency access.

TCP

Transmission Control Protocol.

TF-A

Trusted Firmware-A, the Arm reference secure-monitor firmware executed below EL2 on the APU.

TFTP

Trivial File Transfer Protocol.

TLS

Transport Layer Security.

TPM

Trusted Platform Module, a hardware or firmware secure crypto-element accessed via the TCG TPM 2.0 specification. UEFI/EFI systems expose one via the EFI_TCG2_PROTOCOL.

TRD

TRDs

Targeted Reference Design, an AMD per-board demo bundle that pairs a hardware design with example software.

TRM

Technical Reference Manual.

TTC

TTCs

Triple Timer Counter, a Zynq peripheral providing three independent 16-bit counters.

UART

Universal Asynchronous Receiver-Transmitter.

UARTPS

Zynq Processing System UART IP block.

UDP

User Datagram Protocol.

UEFI

Unified Extensible Firmware Interface.

UFS

Universal Flash Storage, the JEDEC-defined high-performance flash storage interface used in mobile and embedded systems.

UID

User Identifier.

UIO

Userspace I/O, the Linux kernel framework that exposes a hardware device’s interrupts and memory regions to a user-space driver.

ULPI

UTMI+ Low Pin Interface, the MIPI-defined interface between a USB controller and an external USB PHY.

UPIU

UFS Protocol Information Unit, the host-to-device request frame defined by the JEDEC UFS specification.

USB

Universal Serial Bus, the host-controller and cabling standard maintained by the USB Implementers Forum.

UUID

Universally Unique Identifier, the 128-bit identifier defined by RFC 4122.

VCU

Video Codec Unit, the H.264 / H.265 video encode / decode hard block on Zynq UltraScale+ EV devices.

VDU

Video Decode Unit, the H.264 / H.265 video decode hard block on AMD Versal AI Edge devices.

VLAN

Virtual Local Area Network, the IEEE 802.1Q mechanism for partitioning a single physical Ethernet network into multiple logical broadcast domains.

VNC

Virtual Network Computing, a graphical desktop-sharing protocol.

WDT

Watchdog Timer.

WFI

Wait For Interrupt, the Arm assembly instruction that puts the core into a low-power state until an interrupt is received.

WIC

Image format produced by Yocto’s wic tool, used for SD-card and eMMC boot images.

WWDT

Window Watchdog Timer, a watchdog variant that requires the software refresh to land inside a defined time window.

XDMA

DMA/Bridge Subsystem for PCIe, AMD’s PCIe-attached DMA engine driven by the open-source Xilinx XDMA Linux driver.

XEN

The Xen Project hypervisor, used in EDF Platform images to partition Versal devices into multiple guest domains.

XMPU

Xilinx Memory Protection Unit, the per-region access control block on Zynq UltraScale+ that enforces master / address isolation.

XPR

Vivado project file (.xpr).

XRT

Xilinx Runtime, the open-source runtime library and driver stack for managing AMD adaptive SoC and Alveo accelerators.

XSA

Xilinx Shell Archive, the Vivado export format that hands off hardware-design metadata to the SDK / SDTGen.

XSCT

Xilinx Software Command-line Tool, the Tcl-based CLI from the classic SDK / Vitis hardware-handoff flow. PetaLinux projects created against an XSA (the pre-SDT flow) use petalinux-config --get-hw-description to ingest the XSCT-generated outputs.

XSDB

Xilinx System Debugger CLI, the JTAG-attached debug shell built on top of XSCT.

ZDMA

The Zynq DMA controller family, with concrete instances ADMA (LPD) and GDMA (FPD).