Device Specific Specifications and Information
This page contains specification and architecture information for the AMD Embedded Development Framework (EDF) that is applicable to specific device families, series, or portfolio.
AMD Versal Embedded Common Platform CED and PS Specifications
AMD Versal AI Edge series Gen 2 Embedded Common Platform CED and PS Specifications
This specification inherits from the common specification, but also has evaluation board specific items. See also the following:
PS Settings
The following default PS configuration is implemented in the embedded common platform CED for Versal AI Edge series Gen 2, and is aligned with common specifications. There are also some board defined items such as fixed MIO, clocks, and enabling clock frequencies enabled by the speed grade of the target device.
See Board Specific Settings - Board specific specifications and information
MIO Controller - All MIO controllers (for example, I2C, SPI) associated with fixed peripherals of the platform is enabled and configured based on the hardware board design.
MIO I/O Configurations - All MIO default I/O controls (for example, pull-ups, slew rates) is based on the hardware platform design.
Secondary Boot - Is set to
None. This reflects PLM PDI load from the secondary device, but in context of EDF secondary boot devices for boot, Linux is managed by U-Boot and not the PLM.The CIPS configuration enables the defined set of IPI to enable agreed software payloads such as XEN. See the Board and Family specific CED specification pages for the per platform mappings. Board specific specifications and information
NoC + AIE Path Configuration
The AIE hard block IP is to be instantiated and connected in the embedded common platform CED to provide the configuration path to the AIE array as well as the NoC connectivity required to support the “Segmented Configuration” flow.
The overall NoC configuration of the embedded common platform CED is also maintained for users to re-generate PL designs that is compatible with the platform boot firmware. This requires that a static NoC path configuration be maintained as part of the CED.
The CIPS configuration enables the full set of PS-NoC Master interfaces to enable all paths in the boot configuration.
Interrupts
PS-PL Interrupts
The embedded common platform CED enables one LPD interrupt (LPD INT0) and one FPD (FPD INT0) interrupt.
The following table outlines the planned application mapping and utilization of the PS-PL interrupts. TRD application PL designs incrementally enable the PS-PL interrupts as required.
Note: These allocations are not fixed/static in the silicon design but a “template” to minimize differences across AMD owned reference designs. Mappings are shared for TRDs and SLT Designs.
Domain |
IRQ |
Enabled |
Allocation |
AMD Example Designs - Linux |
AMD Example Designs - BM |
|---|---|---|---|---|---|
0 |
Yes |
ISP0 Functions |
visp_ss_0/tile0_isp_isr_irq |
visp_ss_0/tile0_isp_isr_irq |
|
1 |
Yes |
ISP0 Functions |
visp_ss_0/tile0_isp_xmpu_interrupt |
visp_ss_0/tile0_isp_xmpu_interrupt |
|
2 |
Yes |
ISP0 Functions |
visp_ss_0/tile0_isp0_fusa_irq |
visp_ss_0/tile0_isp0_fusa_irq |
|
3 |
Yes |
ISP0 Functions |
visp_ss_0/tile0_isp0_isp_irq |
visp_ss_0/tile0_isp0_isp_irq |
|
4 |
Yes |
ISP0 Functions |
visp_ss_0/tile0_isp1_fusa_irq |
visp_ss_0/tile0_isp1_fusa_irq |
|
5 |
Yes |
ISP0 Functions |
visp_ss_0/tile0_isp1_isp_irq |
visp_ss_0/tile0_isp1_isp_irq |
|
6 |
Yes |
ISP1 Functions |
visp_ss_0/tile1_isp_isr_irq |
||
7 |
Yes |
ISP1 Functions |
visp_ss_0/tile1_isp_xmpu_interrupt |
||
8 |
Yes |
ISP1 Functions |
visp_ss_0/tile1_isp0_fusa_irq |
||
9 |
Yes |
ISP1 Functions |
visp_ss_0/tile1_isp0_isp_irq |
||
10 |
Yes |
ISP1 Functions |
visp_ss_0/tile1_isp1_fusa_irq |
||
11 |
Yes |
ISP1 Functions |
visp_ss_0/tile1_isp1_isp_irq |
||
12 |
Yes |
ISP2 Functions |
visp_ss_0/tile2_isp_isr_irq |
vmix_frmbuf_rd_ss/v_frmbuf_rd_0/interrupt |
|
13 |
Yes |
ISP2 Functions |
visp_ss_0/tile2_isp_xmpu_interrupt |
vmix_frmbuf_rd_ss/v_frmbuf_rd_1/interrupt |
|
14 |
Yes |
ISP2 Functions |
visp_ss_0/tile2_isp0_fusa_irq |
||
15 |
Yes |
ISP2 Functions |
visp_ss_0/tile2_isp0_isp_irq |
frmbuf_wr_ss/v_frmbuf_wr_0/interrupt |
|
16 |
Yes |
ISP2 Functions |
visp_ss_0/tile2_isp1_fusa_irq |
frmbuf_wr_ss/v_frmbuf_wr_1/interrupt |
|
17 |
Yes |
ISP2 Functions |
visp_ss_0/tile2_isp1_isp_irq |
frmbuf_wr_ss/v_frmbuf_wr_2/interrupt |
|
18 |
Yes |
PL Apps |
frmbuf_rd_ss |
frmbuf_wr_ss/v_frmbuf_wr_3/interrupt |
|
19 |
Yes |
PL Apps |
frmbuf_wr_ss |
||
20 |
Yes |
PL Apps |
vmix_ss |
vmix_ss |
|
21 |
Yes |
PL Apps |
axi_timer_hdmi |
axi_timer_hdmi |
|
22 |
Yes |
PL Apps |
v_hdmi_txss1 |
v_hdmi_txss1 |
|
23 |
Yes |
PL Apps |
hdmiphy_ss_0/hdmi_gt_controller |
hdmiphy_ss_0/hdmi_gt_controller |
|
0 |
Yes |
PL Apps |
pl_axi_intc (for MIPI interrupts) |
||
1 |
Yes |
PL Apps |
VCU - IRQ_ERROR |
||
2 |
Yes |
PL Apps |
VCU _ Decoder |
||
3 |
Yes |
PL Apps |
VCU_Encoder |
||
4 |
Yes |
PL Apps |
mipi_rx (0XB100_0000) |
||
5 |
Yes |
PL Apps |
mipi_rx (0XB106_0000) |
||
6 |
Yes |
PL Apps |
axi_iic_hdmi |
axi_iic_hdmi |
|
7 |
Yes |
PL Apps |
hdmi_rxss |
hdmi_rxss |
IPI Mappings
The embedded common platform CED enables a superset of IPI mappings to support current and future TRDs and are defined in the following table.
These do not impact the PS/PL boundary so are not controlled relative to TRD specific PL designs.
Enabled |
Master |
Description |
|
|---|---|---|---|
Yes |
Platform management functions |
||
Yes |
Platform management functions |
||
Yes |
Security management functions |
||
IPI 0 |
Yes |
A78_0 |
APU SW to map functions |
IPI 1 |
Yes |
R52_0 |
RPU SW/RTOS function (TBD) |
IPI 2 |
Yes |
A78_0 |
APU SW to map functions |
IPI 3 |
Yes |
A78_0 |
APU SW to map functions |
IPI 4 |
Yes |
A78_0 |
APU SW to map functions |
IPI 5 |
Yes |
A78_0 |
APU SW to map functions |
IPI 6 |
Yes |
A78_0 |
APU SW to map functions |
IPI NOBUF 1 |
Yes |
A78_0 |
OpenAMP example app (APU) |
IPI NOBUF 2 |
Yes |
R52_0 |
OpenAMP example app (RPU) |
IPI NOBUF 3 |
Yes |
R52_6 |
ISP support functions |
IPI NOBUF 4 |
Yes |
R52_7 |
ISP support functions |
IPI NOBUF 5 |
Yes |
R52_8 |
ISP support functions |
IPI NOBUF 6 |
Yes |
R52_9 |
ISP support functions |
System Level Memory Map
The system level memory map aligns with the AMD EDF System Memory map standard Common Specifications
The implementation is dependent on the hard IP locations within a devices global address map, which are defined in the relevant Technical Reference Manual
Versal Adaptive SoC Technical Reference Manual (AM011)
The first table captures a high-level summary from AM011 on key sections and offsets for defining the system level DDR memory map
Start Addr |
Description |
|---|---|
0x000 0000 0000 |
DDRMC0 - Region 0 |
0x000 8000 0000 |
Versal internal memory maps |
0x008 0000 0000 |
DDRMC0 - Region 1 |
0x0C0 0000 0000 |
DDRMC0 - Region 2 |
0x100 0000 0000 |
DDRMC0 - Region 3 |
0x200 0000 0000 |
AIE Memory Map |
0x201 0000 0000 |
PL Memory Map |
0x400 0000 0000 |
PS-PL Memory Map |
0x500 0000 0000 |
DDRMC1 - Region 0 |
0x580 0000 0000 |
DDRMC1 - Region 1 |
0x600 0000 0000 |
DDRMC2 - Region 0 |
0x680 0000 0000 |
DDRMC2 - Region 1 |
0x700 0000 0000 |
DDRMC3 - Region 0 |
DDR Memory Map
The Memory Map is built based on the AMD EDF System Memory map standard Common Specifications
The following table represents the VEK385 specific map, reflecting the number of RPUs and physical memory available in the platform.
See AMD EDF Board specific specifications and information / flows for per Evaluation board implementation
Start Addr |
Size (MB) |
Description |
Fixed/Variable |
XMPU |
|---|---|---|---|---|
Low DDR - 2 GB |
||||
0x000 0000 0000 |
16 |
Versal PLM |
Fixed |
Yes - PLM FW |
0x000 0100 0000 |
6 |
TF-A - Transfer list / handoffs |
Fixed |
TBD |
0x000 0160 0000 |
2 |
TF-A - Core runtime memory |
Fixed |
Yes - TF-A FW |
0x000 0180 0000 |
128 |
OP-TEE shared buffers & dynamic TAs |
Fixed |
Yes - Secure OS/Secure Partition |
0x000 0980 0000 |
8 |
RPU Core 0-1 OpenAMP allocations (4 MB / core) |
x2 RPU Cores |
Yes - RPU |
32 |
Free memory |
|||
0x000 0C00 0000 |
320 (400 MB requested) |
RPU+:term:ISP reservation |
x3 ISP |
Yes - RPU |
0x000 2000 0000 |
1536 |
Linux - Low DDR |
LOW_DDR Remainder |
No |
High DDR |
||||
0x008 0000 0000 |
2048 |
ISP frame buffer allocation (DDRMC closest to ISPs) |
Scale # ISPs |
|
Platform dependent |
Linux - High DDR |
HIGH_DDR Remainder |
||
Platform dependent |
PL & AIE dedicated allocations |
RPU configuration
In the embedded common platform CED, the RPU is set up in a “split” mode of operation. The application mapping by cluster and core is defined in the following table.
Cluster |
Function |
|
|---|---|---|
0 |
0 |
RTOS based OpenAMP app |
0 |
1 |
Bare-metal “hello world” app |
1 |
2 |
Unused |
1 |
3 |
Unused |
2 |
4 |
Unused |
2 |
5 |
Unused |
3 |
6 |
ISP Support (3 Tiles) |
3 |
7 |
ISP Support (3 Tiles) |
4 |
8 |
ISP Support (3 Tiles) |
4 |
9 |
ISP Support (3 Tiles) |
TCM
The common CED enables TCM “Cluster All” with ECC enabled.
The TCM associated with each RPU cluster is allocated to the corresponding application SW running on that cluster.
OCM
The embedded common platform CED enables all OCM with ECC enabled.
The OCM is allocated to the RPU subsystem for the ISP support functionality.
Timer Counter (AMD TTC) Assignments
The following table defines the TTC utilization with the embedded common platform CED, the CED only handles the enablement of the noted TTCs and mapping is handled by the downstream tools.
Owner |
Function |
|
|---|---|---|
0 |
A78_* |
Fan Control - Waveout on VEK385 PMC-MIO 49 |
1 |
A78_* |
Reserved for future use |
2 |
R52_0 |
Zephyr tick counter |
3 |
R52_1 |
Reserved for future use |
4 |
R52_6 |
FreeRTOS/SafeRTOS tick counter for ISP FW |
5 |
R52_7 |
FreeRTOS/SafeRTOS tick counter for ISP FW |
6 |
R52_8 |
FreeRTOS/SafeRTOS tick counter for ISP FW |
7 |
R52_9 |
FreeRTOS/SafeRTOS tick counter for ISP FW |
PS-PL Clocks
The embedded common platform CED defines the following default PS-PL clock interfaces:
Clk |
Frequency |
Function |
|---|---|---|
PL CLK0 |
100 MHz |
Feed clock wizard for PL clock generation |
Linux Kernel and RootFS Configuration
See the Common Specification pages - Common Specifications
AMD Versal AI Core and AI Edge series Embedded Common Platform CED and PS Specifications
PS Specifications:
The following default PS configuration is implemented in the embedded common platform CED for Zynq Ultrascale+, and is aligned with common specifications, there are also some board defined items such as fixed MIO, clocks, and enabling clock frequencies enabled by the speed grade of the target device.
PS Peripheral mappings in the CED
AXI BRAM Controller: Mapped to the address range for Block RAM access.
AXI GPIO (gpio_0): Mapped to EMIO interface with 256 GPIO signals.
AXI GPIO (gpio_1): Mapped to EMIO interface with 256 additional GPIO signals.
AI Engine: Mapped to a configurable address space for AI processing.
Master NoC: Mapped to system’s AXI address space for interconnectivity.
AXI NoCs: Mapped to address range facilitating access between different IP blocks.
Clocking Wizard: Mapped to the address space for clock signal management.
Timers: Mapped to EMIO interface with event generation capabilities.
DDR Memory Interfaces: Mapped to the address space connecting LPDDR4 memory.
I2C (0): Mapped to MIO pins for connecting to external devices (specific pins per design).
UART (Serial Communication): Mapped to MIO pins for serial data transfer (specific pins per design).
SPI (Serial Peripheral Interface): Mapped to MIO pins for SPI connections (specific pins per design).
Interrupts
PS-PL Interrupts
The embedded common platform CED enables one LPD interrupt.
The following table outlines the planned application mapping and utilization of the PS-PL interrupts.
Domain |
IRQ |
Enabled |
Allocation |
|---|---|---|---|
0 |
Yes |
PL Interrupts |
IPI Mappings
The embedded common platform CED enables a superset of IPI mappings to support current and future TRDs and are defined in the following table.
These do not impact the PS/PL boundary so are not controlled relative to TRD specific PL designs.
IPI / IRQ |
Enabled |
Master |
Description |
|---|---|---|---|
Yes |
|||
Yes |
|||
Yes |
IPI used by PSM (Platform Service Manager) for event signaling. |
||
IPI 0 |
Yes |
A72 |
|
IPI 1 |
Yes |
R5 0 |
Used by RPU core 0 for inter-core communication. |
IPI 2 |
Yes |
R5 1 |
Used by RPU core 1 for inter-core communication. |
IPI 3 |
Yes |
A72 |
|
IPI 4 |
Yes |
A72 |
|
IPI 5 |
Yes |
A72 |
|
IPI 6 |
Yes |
A72 |
DDR Memory Map
The following represents the map reflecting the number of RPUs and physical memory available in the platform.
Region Name |
Start Address |
Size (Bytes) |
Description |
|---|---|---|---|
C0_DDR_LOW0 |
0x0000_0000 |
2 GB |
DDR region on Controller 0, Channel 0 |
C0_DDR_LOW1 |
0x8000_0000 |
2 GB |
DDR region on Controller 0, Channel 1 |
C1_DDR_CH1 |
0x5000_0000_0000 |
4 GB |
DDR region on Controller 1, Channel 1 |
C1_DDR_CH2 |
0x6000_0000_0000 |
4 GB |
DDR region on Controller 1, Channel 2 |
C2_DDR_LOW0 |
0x0000_0000 |
2 GB |
DDR region on Controller 2, Channel 0 |
C2_DDR_LOW1 |
0x8000_0000 |
2 GB |
DDR region on Controller 2, Channel 1 |
C3_DDR_LOW0 |
0x0000_0000 |
2 GB |
DDR region on Controller 3, Channel 0 |
C3_DDR_LOW1 |
0x8000_0000 |
2 GB |
DDR region on Controller 3, Channel 1 |
C1_DDR_LOW0 |
0x0000_0000 |
2 GB |
DDR region on Controller 1, Channel 0 (LPD NOC) |
C1_DDR_LOW1 |
0x8000_0000 |
2 GB |
DDR region on Controller 1, Channel 1 (LPD NOC) |
System Level Memory Map
Start Address |
Description |
|---|---|
0x0000_0000 |
DDR C0 LOW0 |
0x8000_0000 |
DDR C0 LOW1 |
0xA400_0000 |
AXI BRAM Controller |
0xA600_0000 |
AXI GPIO 0 |
0xA601_0000 |
AXI GPIO 1 |
0x2000_0000_0000 |
AI Engine Memory Space |
0x5000_0000_0000 |
DDR C1 CH1 |
0x6000_0000_0000 |
DDR C1 CH2 |
0xFFFC_0000 |
OCM |