1/*
2 * Copyright (c) 2024 Advanced Micro Devices, Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7
8#include <zephyr/drivers/i2c.h>
9#include <zephyr/logging/log.h>
10
11LOG_MODULE_REGISTER(main, LOG_LEVEL_INF);
12
13#define I2C_MUX_ADDR 0x74
14#define I2C_MUX_CHANNEL 0x01U
15static const struct device *const axi_i2c1_dev = DEVICE_DT_GET(DT_NODELABEL(axi_i2c1));
16
17static int32_t axi_i2c_master_init(void)
18{
19 int32_t ret = 0;
20
21 LOG_INF("AXI-I2C: master: init: Start");
22
23 if (device_is_ready(axi_i2c1_dev) == false) {
24 LOG_INF("AXI-I2C: master: device is NOT_READY");
25 ret = -ENODEV;
26 goto out;
27 }
28 LOG_INF("AXI-I2C: master: device READY");
29
30out:
31 if (ret == 0) {
32 LOG_INF("AXI-I2C: master: init: PASSED");
33 } else {
34 LOG_INF("AXI-I2C: master: init: FAILED");
35 }
36
37 return ret;
38}
39
40static int32_t axi_i2c_master_write(void)
41{
42 int32_t ret;
43 uint8_t datas[6];
44
45 LOG_INF("AXI-I2C: master: write: Start");
46
47 datas[0] = I2C_MUX_CHANNEL;
48 LOG_INF("AXI-I2C: master: write: I2C_MUX_ADDR: Progress");
49 LOG_INF("AXI-I2C: master: write: data: %02Xh", datas[0]);
50 ret = i2c_write(axi_i2c1_dev, datas, 1, I2C_MUX_ADDR);
51 if (ret != 0) {
52 LOG_INF("AXI-I2C: master: write: I2C_MUX_ADDR FAILED, ret:%d", ret);
53 goto out;
54 }
55 LOG_INF("AXI-I2C: master: write: I2C_MUX_ADDR success");
56
57out:
58 if (ret == 0) {
59 LOG_INF("AXI-I2C: master: write: PASSED");
60 } else {
61 LOG_INF("AXI-I2C: master: write: FAILED");
62 }
63
64 return ret;
65}
66
67static int32_t axi_i2c_master_read(void)
68{
69 int32_t ret;
70 uint8_t datas[6];
71
72 LOG_INF("AXI-I2C: master: read: Start");
73
74 LOG_INF("AXI-I2C: master: read: I2C_MUX_ADDR Progress");
75 (void)memset(datas, 0, sizeof(datas));
76 ret = i2c_read(axi_i2c1_dev, datas, 3, I2C_MUX_ADDR);
77 if (ret != 0) {
78 LOG_INF("AXI-I2C: master: read: IIC_SLAVE_ADDR FAILED, ret:%d", ret);
79 goto out;
80 }
81 LOG_INF("AXI-I2C: master: read: I2C_MUX_ADDR success");
82 LOG_INF("AXI-I2C: master: read: data: %02Xh %02Xh %02Xh", datas[0], datas[1], datas[2]);
83
84out:
85 if (ret == 0) {
86 LOG_INF("AXI-I2C: master: read: PASSED");
87 } else {
88 LOG_INF("AXI-I2C: master: read: FAILED");
89 }
90
91 return ret;
92}
93
94static int axi_i2c_master_writeread_repstart(void)
95{
96 int ret;
97 uint8_t wr_datas[6];
98 uint8_t rd_datas[6];
99
100 LOG_INF("AXI-I2C: master: write-read-repeated-start: Start");
101
102 LOG_INF("AXI-I2C: master: write-read-repeated-start: IIC-Mux Progress");
103 wr_datas[0] = I2C_MUX_CHANNEL;
104 LOG_INF("AXI-I2C: master: write-repeated-start: data: %02Xh", wr_datas[0]);
105 (void)memset(rd_datas, 0, sizeof(rd_datas));
106 ret = i2c_write_read(axi_i2c1_dev, I2C_MUX_ADDR, wr_datas, 1, rd_datas, 1);
107 if (ret != 0) {
108 LOG_INF("AXI-I2C: master: write-read-repeated-start: IIC-Mux FAILED, ret:%d", ret);
109 goto out;
110 }
111 LOG_INF("AXI-I2C: master: write-read-repeated-start: IIC-Mux success");
112 LOG_INF("AXI-I2C: master: write-read-repeated-start: read data: %02Xh", rd_datas[0]);
113
114out:
115 if (ret == 0) {
116 LOG_INF("AXI-I2C: master: write-read-repeated-start: PASSED");
117 } else {
118 LOG_INF("AXI-I2C: master: write-read-repeated-start: FAILED");
119 }
120
121 return ret;
122}
123
124static void axi_i2c_master_mode_test(void)
125{
126 int32_t ret;
127
128 /* AXI-I2C master init */
129 ret = axi_i2c_master_init();
130 if (ret != 0) {
131 goto out;
132 }
133
134 /* AXI-I2C master-write */
135 ret = axi_i2c_master_write();
136 if (ret != 0) {
137 goto out;
138 }
139
140 /* AXI-I2C master-read */
141 ret = axi_i2c_master_read();
142 if (ret != 0) {
143 goto out;
144 }
145
146 /* AXI-I2C master-write-read-repeated-start */
147 ret = axi_i2c_master_writeread_repstart();
148 if (ret != 0) {
149 goto out;
150 }
151
152out:
153 if (ret != 0) {
154 LOG_INF("AXI-I2C: master: mode-test completed, FAILED");
155 } else {
156 LOG_INF("AXI-I2C: master: mode-test completed, PASSED");
157 }
158}
159
160int main(void)
161{
162 /* master usecase */
163 axi_i2c_master_mode_test();
164
165 return 0;
166}